As is well known, the evolution of the electrical characteristics of processors for PCs, workstations, and servers obliges manufacturers to study new, more flexible and economic solutions for supplying various peripherals such as DDR and DDR2 memory banks, chipsets, graphic boards, etc.
At present, the flexibility and cost criteria orient the research toward solutions that are capable of adapting to the different segments of use which are characterized by a variety of input supply voltages (buses of 12V, 5V, and 3.3V are the most common) and output supply voltages (for example, 2.5V and 1.25V for DDR memories, 1.8V and 0.9V for DDR2 memories, 1.8V or 1.5V for chipsets; and 1.7V-1.3V for the GPU processor of graphic boards).
Also the required currents vary enormously, especially for different end uses, such as for desktops of the performance, main stream, and value types, servers of the high end and low end types, etc.
It is known that the most efficient and least expensive system for realizing DC-DC converters of the high current switching type is the multi-phase system shown in FIG. 1, in which the current of each phase is generally set in a range of 15 to 30 A. For low current applications (<15 A), the single-phase switching converter is the most advantageous choice from the economic point of view.
The known multi-phase converter uses a classical control system of the peak current mode type for each phase. The main advantage of a current mode system is due to the fact that, if each phase uses the same control method, when multiple DC-DC converters are placed in parallel in multi-phase, the desired current sharing is obtained automatically, saving valuable resources in terms of package pins and occupied silicon area.
In fact, the choice of current mode systems seems to even be an inescapable choice.
Although advantageous under several aspects, these peak current mode systems show a load effect. That is, when the output load (i.e., the current) varies, the output voltage is set not at the desired regulation value but at a new value which diverges from the one set on the basis of the choice of some parameters, both internal and external, of the device.
In the supply systems of CPU processors this effect is desired and is known as “droop” or “voltage positioning effect”, but the processor performance and reliability depend on its accuracy.
However, for ensuring this desired effect, particular control techniques are necessary. Unfortunately, in current mode systems such as the peak current mode, this load effect is not at all accurate and can show a variance up to 50%.
If a DC-DC converter were designed with the purpose of minimizing this effect, the resulting current sharing would be unsatisfactory when multiple phases are associated in parallel.
Moreover, the peak current mode has a minimum working duty cycle D below which it cannot operate and which thus limits the range of applications since Vout=D×Vin.
For reading the phase current, it is necessary to use two pins (those connected across the inductance) and thus if there are plural phases in parallel the number of pins remarkably increases.
To limit the number of pins to a maximum of twenty-eight, the integrated drivers turn on and off the power MOS transistors of the highside driver type taking, as reference, not so much the phase nodes as directly the ground potential.
This operation saves two pins but can be very dangerous since it can generate false non-controlled turns-on of the power MOS transistors.
Thus, control systems with current mode DC-DC converters, in particular of the peak current mode type, show the following advantages: intrinsic current sharing, and reading inductance current with a clean signal and continuous time; and the following disadvantages: load effect, minimum Duty Cycle, two pins per phase to read the inductance current, power MOS transistors referred to ground rather than to phase, and lack of a PGOOD signal.
A known technical solution trying to overcome these drawbacks is incorporated in a converter commercially known as the “Intersil ISL644x”, which is manufactured by Intersil.
In this device the problem of the load effect is overcome due to a control of the current mode type, however not of the peak current mode type, and the phase current is read due to the voltage fall on the power transistors of the Lowside and subsequently sampled by erasing the current ripple.
In this way, a single pin (the phase one) is enough for reading the current on the Lowside, which is measured with respect to the ground of the controller rather than on the source terminal of the Lowside.
The problem of this known device is that, due to the lack of pins, the compensation network is integrated and the switching frequency is not programmable. Therefore, the desired flexibility is substantially lost in the resulting lack of package resources.
Moreover, the use of the information of the current taken from the voltage fall across the Lowside implies that this information is sampled (in the track&hold mode) when the Lowside is turned on and maintained when the Lowside is turned off. This eliminates, or strongly reduces, the current ripple, but, being that the power drivers are integrated in the same device, there is the risk that the beginning of the hold of the current information already sampled (hold) occurs in correspondence with a transition of the driver (usually also drivers of the remaining phases). The hold of the information temporarily stores switch noise and generates a malfunction of the whole system, which is known as “crossnoise”.
Therefore, this known solution shows the following drawbacks: inner and little flexible compensation network, maximum duty cycle limited at 70% to ensure the reading of the current on Lowside, non-programmable switching frequency, and inner crossnoise.
A second known solution is known as the “NCP5425” controller of On Semiconductor, which integrates two voltage-mode controllers and realizes the current sharing by using the error amplifier of a second controller, whose pins are all available.
This technique allows management of the current sharing but not programming of the distribution of the currents in the phases unless different sense resistances are available.
The current reading occurs on the inductance and not on the Lowside power transistors. This makes the circuitry necessary for preventing crossnoise problems and for sampling the signal superfluous.
However, the drawback of this controller is in the drivers, which supply only 4V at the maximum driving for applications with Vin of 12V. Moreover, power Highside driver transistors are driven towards the device ground, which is unique and in common both for the analog and power part.